Agilent Technologies 54645A Manuel d'instructions télécharger pdf (Page 80)

Limit Test Event Register (LTER)

Bit 0 (COMP) of the Limit Test Event Register is set when the Limit Test

completes. The Limit Test completion criteria are set by the LTESt:RUN

command.

Bit 1 (FAIL) of the Limit Test Event Register is set when the Limit Test fails.

Failure criteria for the Limit Test are defined by the LTESt:FAIL command.

The Limit Test Event Register is read and cleared with the LTER? query.

When either the COMP or FAIL bits are set, they in turn set the LTEST bit

(bit 8) of the Operation Status Register. You can mask the COMP and FAIL

bits, thus preventing them from setting the LTEST bit, by defining a mask

using the LTEE command.

Enable Mask Value

Block COMP and FAIL 0

Enable COMP, block FAIL 1

Enable FAIL, block COMP 2

Enable COMP and FAIL 3

Status Reporting

Limit Test Event Register (LTER)

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Agilent Technologies 54645A Manuel d'instructions Page 80