Agilent Technologies N5980A Manuel d'utilisateur Page 1

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Agilent J-BERT N4903B
High-Performance Serial BERT
7 Gb/s and 12.5 Gb/s
Data Sheet Version 1.1 (Extended SSC and 14.2 Gb/s)
Complete jitter tolerance test
for embedded and
forwarded clock devices
• Integrated
• Calibrated
• Automated
• Compliant
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Résumé du contenu

Page 1 - High-Performance Serial BERT

Agilent J-BERT N4903BHigh-Performance Serial BERT7 Gb/s and 12.5 Gb/sData Sheet Version 1.1 (Extended SSC and 14.2 Gb/s)Complete jitter tolerance test

Page 2

Specifi cations-Pattern GeneratorData output and auxiliary data output (DATA OUT, AUX DATA OUT)Table 2. Output characteristics for J-BERT N4903B genera

Page 3 - J-BERT N4903B

11Pattern Generator Specifi cationsClock output (CLK OUT)Clock can operate at full bit-rate or at half bit-rate (Option 003) to support testing of forw

Page 4

12Error add input (ERROR ADD)The external error add input adds a single error to the data output for each rising edge at the input. When electrical id

Page 5

13Library of pre-defi ned patternsMany popular compliance patterns are predefined, such as: CJTPAT, CJPAT, DisplayPort, FDDI, Fibre Channel, K28.5, PCI

Page 6 - Jitter Tolerance Tests

14Jitter Tolerance Test Specifi cationsThe built-in jitter sources are designed to cover DisplayPort, PCI Express, SATA, USB3, Fibre Channel, QPI, Hype

Page 7 - Eye contour

15Sinusoidal jitter (Option J10)This injects sinusoidal jitter in the lower frequency range with multiple UIs. Table 12. Specifi cations for sinusoidal

Page 8 - User Interface

16Bounded uncorrelated jitter (Option J10)This injects a high probability jitter using a PRBS generator and low-pass filters. Table 14. Specifi cation

Page 9

17Jitter Tolerance Test Specifi cationsFigure 23. Interference channel connectorsFigure 24. Typical S21 parameter for ISI channel of 9 inch lengthTable

Page 10

18Error Detector Specifi cationsData inputs (DATA IN)Table 19. Specifi cations for error detectorRange of operation 150 Mb/s to 12.5 Gb/s (Option C13)15

Page 11 - Clock input (CLK IN)

19Table 22. Specifi cations for tunable loop bandwidthTunable loop bandwidth 500 kHz to 12 MHz for data rates 1.46 Gb/s to 12.5 Gb/s 100 kHz to 4 MHz f

Page 12

Agilent Technologies N4900 SeriesAgilent offers a wide range of serial bit error ratio test (BERT) solutions for R&D and manufacturing. The J-BERT

Page 13

20Error Detector Specifi cationsTrigger output (TRIG OUT)Pattern trigger modeThis provides a trigger synchronized with the selected error detector refe

Page 14 - Periodic jitter (Option J10)

21Auxiliary output (AUX OUT)This output can be used to provide either clock or data signals:Clock: clock signals from the input or the recovered clock

Page 15 - Random jitter (Option J10)

22Mainframe CharacteristicsFigure 29. Rear panel viewTable 28. General mainframe characteristicsOperating temperature 5 ºC to 40 ºC (-23 to +104 ºF)St

Page 16 - Total jitter

23Ordering InstructionsJ-BERT N4903B high-performance serial BERTIncludes six 50-Ω SMA terminations, ten adaptors 3.5 mm female to 2.4 mm male, commer

Page 17

24Ordering InstructionsTable 31. Recommended accessoriesRecommended accessories Description Model numberCables, adapters2.4 mm matched pair cable N491

Page 18 - Error Detector Specifi cations

25Title Publication numberJ-BERT N4903A High-Performance Serial BERT Brochure5989-3882ENBit Recovery Mode for Characterizing Idle and Framed Data Traf

Page 19

Remove all doubtOur repair and calibration services will get your equipment back to you, performing like new, when prom-ised. You will get full value

Page 20

3Figure 1. J-BERT is the highest-performance BERT amongst Agilent‘s offering of serial BERT solutions for R&D and manufacturingR&D characteriz

Page 21

4 J-BERT N4903B High-Performance Serial BERTThe J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedd

Page 22 - Mainframe Characteristics

5J-BERT N4903B The Most Complete Jitter Tolerance Test SolutionKey NEW Capabilities of J-BERT N4903B• Supports testing of forwarded clock devices: ha

Page 23 - Ordering Instructions

6Calibrated and integrated jitter injection• Periodic jitter, single and dual-tone (Option J10)• Sinusoidal jitter (Option J10)• Random jitter and

Page 24 - Accessories

7User Interface and Measurement SuiteQuick eye diagram and maskingThe quick eye diagram allows a one-shot check for a valid signal. Due to the higher

Page 25 - Related Literature

8User InterfaceBit recovery mode (Option A01)This mode is useful for analyzing non-deterministic traffic. This is helpful when you need to analyze rea

Page 26 - Revised: October 1, 2009

9Figure 14. Pattern generator setup screen with graphical display of signal levels and data-to-clock delaySpecifi cations-Pattern GeneratorFigure 13. G

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