Agilent Technologies C-Size VXIbus Systems Manuel d'utilisateur Page 81

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I (continued)
Interrupt
circuitry, 43
configuring for, 57
interface, 10
priority, 10, 24, 43, 57
request levels, 43, 57
requests, generating, 57
using, 57
Inverse Logic, 8
IRQ
ACKNOWLEDGE input line, 43, 57
jumper, 24, 43, 57
REQUEST output line, 43, 57
J
Jumpers, interrupt priority, 24, 43, 57
L
LADDR, 23
LATCH, 55
output low, 42
LATCH*, 40
Lead Length, 11, 17
Logical Address, 23
LWORD*, 34
M
Mainframe
cooling requirements, 22
installing breadboard, 25
Maximum
component height, 11, 63
component lead length, 11, 17, 63
power dissipation, 63
Metal Standoffs, 20 - 21
Mnemonic Asterisk Suffix, 8, 32
O
Option A3E, 11, 27
P
Parts List, 65 - 66
PC Board Standoffs, 20 - 21
PIACK*
enabling buffer U10, 57
true, 44, 57
Power Supply, 10
backplane voltages available, 63
pin numbers, 47
using other, 60
voltage, 47, 60
R
READ*, 36, 52
Reading
custom register, 62
data from registers, 51
device type register, 10, 38, 53, 61
ID register, 10, 37, 53, 61
status register, 10, 36, 52 - 53
Registers
control register, 10, 40 - 41, 54 - 56, 61
decoding, 32
device type register, 10, 38, 53, 61
ID register, 10, 37, 53, 61
reading data from, 51
status register, 10, 36, 52 - 53
Reset
hardware, 59
module, 10, 59
signal (SYSRESET), 44, 59
software, 59
S
Safety Warnings, 4, 7, 11, 13
Schematics, 68 - 71
Setting
interrupt priority, 24, 43, 57
logical address switch, 23
Shielded-Twisted-Pair Cable, 27
SHOCK HAZARD, 13
Software Reset, 59
Specifications, 63
compliance, 7
Standoffs, 20 - 21
Static Sensitivity, 13
Status Register
access points, 52
backplane address lines, 52
bit definitions, 36, 51
disabling, 42
enabling, 36
Agilent E1490C User’s Manual Index 75
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