10
Agilent Semiconductor
Process Evaluation Core
Software (SPECS)
Agilent SPECS is a test shell
environment for the Agilent 4070
Series.
Input
User interaction occurs via a
graphical interface with spread-
sheet-like operation. Test plans
require simple specifications:
wafer, die, test, and probe.
Customization
Agilent supplies basic develop-
ment, engineering, and operator
test shell frameworks, which
users can tailor or modify to
create entirely new frameworks.
Analysis & Output
All data is output into a flat
ASCII file which users can
manipulate to allow for input
into database software. In addi-
tion, the data management
structure supports x-y graphs,
histograms, and wafer maps.
UNIX
Users have full access to the
UNIX environment from within
the test shell.
Linux
Users have full access to the
Linux environment from within
the test shell.
System Controller
UNIX
®
Supported Computers
HP Visualize workstation
C3600, C3700B, C3750, C8000
Operating System
HP-UX 11i
For C3600, C3700B, C3750,
BASIC/UX (C.08.04), SICL (11i-
2.1) or C/ANSI C, SICL
For C8000, BASIC/UX(C.08.10),
SICL (11i-2.5) or C/ANSI C, SICL
Recommended Memory: 256 MB
Required Disk
8 GB (forC3600, C3700B, C3750)
20 GB (for C8000)
Linux
Supported Computer
HP xw8400 Workstation
Operating System
RedHat Enterprise Linux WS4
Update3
BASIC/LX (12.2), SICL (3.2) or C/
ANSI C, SICL
Required Memory: 1 GB
Required Disk: 20 GB
Required GP-IB Interfaces
Agilent recommends two exter-
nal GP-IB interface cards for use
with: One for instruments con-
trolled by 4072A TIS commands
(e.g., 3458A) and another for an
automatic wafer prober.
System Software Capabilities
- System Management
- Control of subsystems (TIS
Library)
- Parameter measurement utility
(PARA Library)
- Off-line debugging
- Interactive Debugging Panel
(IDP includes Test Algorithm
Code Generating Function)
- Probing pattern generation and
wafer maps display (PPG, MAP)
- Prober Control Library (Sample
program): Electroglas, TEL,
and TSK
- Application program (Sample
program): Flash memory cell
evaluation, Charge pumping
method
- Automatic Diagnostics
Pulse Force Unit:
HV-SPGU Option
1
Supported Pulse Generators
High-voltage semiconductor
pulse generator unit (HV-SPGU)
modules
Installable HV-SPGU modules: 5 (max.)
Channels per SPGU: 2
Pulse Force Mode
Pulse Signal: Each HV-SPGU
channel supports 2-level and 3-
level pulses
Output Mode
All pulse generator channels (up
to 10) can force synchronously
HV-SPGU Output Impedance: 50 Ω
HV-SPGU Load Impedance
0.1 Ω to 10 MΩ
Pulse Setting Range
Pulse Level (at open load)
±40 V (at 2-level and 3-level)
Pulse Period (at 50 Ω load)
350 ns to 10 s, 10 ns resolution
Pulse Width (at 50 Ω load)
50 ns to [Period − 50 ns] with
2.5 ns
2
or 10 ns
3
resolution
Pulse Delay (at 50 Ω load)
0 s to [Period −75 ns] with 2.5
ns
2
or 10 ns
3
resolution
Transition Time (at 50 Ω load)
20 ns to 400 ms with 2 ns
2
or 8
ns
3
resolution
Transition Time Minimum (at 50 Ω load)
20 ns
4
, 30 ns
5
Pulse Amplitude (at open load)
0 to 80V peak-to-peak
Pulse Resolution (at open load)
0.4 mV (Vout ≤10 V)
1.6 mV (Vout >10 V)
Pulse Level Accuracy (at open load)
± (2% +150 mV)
Pulse Shape Accuracy (at 50 Ω load)
Delay: ± (3% +1 ns)
Transition Time: −5% to (+5% + 35 ns)
Overshoot/Ringing: ± (5% of
amplitude +20 mV)
Skew between pins: ±10 ns
Pulse Shape Accuracy (reference data
at 5 kΩ load)
Transition Time: −5% to (+5% + 35 ns)
Overshoot/Ringing: ± (5% of
amplitude +20 mV)
Skew between pins: ±10 ns
1
Requires Linux system controller
2
Transition time setting ≤10 µs
2
Transition time setting >10 µs
4
|Vamp | ≤10 V (to 50 Ω)
5
10 V < |Vamp| ≤20 V (to 50 Ω)
(428 pages)
(18 pages)
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