Agilent Technologies 54502A Manuel de service télécharger pdf (Page 43)

6. Press RUN. The State Listing is displayed and shows Fs for the channels

under test, when test is passed, as in figure 3-9.

Note To ensure consistent pattern of Fs in listing, use front-panel ROLL field and knob

to scroll through State Listing.

7. If testing the HP 1651B, connect the K clock of Pod 2 to the test connector

and repeat steps 4 and 6 for the falling edge of K clock.

8. Remove the probe tip assembly from the logic analyzer probe cable and

attach to the next logic analyzer probe cable to be tested. Take care not to

dislodge grabbers from the test connector. If testing the HP 1651B then

re-assign the falling edge of J clock.

9. Repeat steps 3, 4, 6 and 7 until all pods have been tested.

10. Disconnect lower eight bits (bits 0 through 7) from test connector. Attach

upper eight bits (bits 8 through 15) to the test connector.

11. Repeat steps 3, 4, 6, 7 and 8 until the upper bits of all pods have been tested.

Figure 3-9. State Listing for Data Test 1

Performance Tests HP 1650B/1651B

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Agilent Technologies 54502A Manuel de service Page 43