Agilent Technologies 54502A Manuel de service télécharger pdf (Page 55)

a. Move cursor to Clock field and SELECT, then assign Mixed Clocks.

b. Assign falling transition of the J clock to Master Clock and rising

transition of the J clock to Slave Clock.

c. Assign channels 0-3 and 8-11 of the pod under test.

d. Set Clock Period to > 60 ns.

5. Set the State Trace Specification without sequencing levels and Count Off

as in previoius figure 3-13.

6. Press RUN. The State Listing displays alternating Fs and 0s for the channels

under test as in figure 3-24.

Note To ensure consistent pattern of alternating Fs and 0s, use the front-panel ROLL

field and knob to scroll through State Listing.

7. Connect the next clock to the test connector and repeat steps 4 and 6.

Repeat until all clocks have been tested (clocks J, K, L, M and N).

8. Remove the probe tip assembly from the logic analyzer probe cable and

attach to the next logic analyzer probe cable to be tested. Take care not to

dislodge grabbers from the test connector.

9. Repeat steps 3, 4, 6 and 7 until all pods have been tested (pods 1 through 5).

Start again with the falling edge of J clock as the Master and rising edge of

the J clock as the Slave clock. Repeat until channels 0 - 3 and 8 - 11 of all

pods have been tested (pods 1 - 5).

10. Disconnect bits 0-3 and bits 8-11 from the test connector. Attach bits 4-7 and

bits 12-15 to the test connector. Repeat steps 3, 4, 6, 7 and 8 until all pods

have been tested (pods 1 through 5).

Figure 3-24. State Listing for Data Test 5

Performance Tests HP 1650B/1651B

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Agilent Technologies 54502A Manuel de service Page 55