Agilent Technologies 54502A Manuel de service Page 62

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6. Press RUN. The timing analyzer acquires data and shows glitches for
channels under test as in figure 3-34. SELECT Delay field and rotate knob
to assure consistent glitch detection.
Note If sample clock and data synchronize, glitches may be displayed on the timing
screen as valid data transitions.
7. Remove the probe tip assembly from the logic analyzer probe cable and
attach to the next logic analyzer probe cable to be tested. Take care not to
dislodge grabbers from the test connector.
8. Repeat steps 3, 4, and 6 until all pods have been tested (pods 1 through 5).
Make sure to assign correct pod to be tested in System Configuration.
9. Disconnect lower eight bits (bits 0 through 7) from test connector. Attach
upper eight bits (bits 8 through 15) to the test connector.
10. Repeat steps 3, 4, 6 and 7 until the upper bits of all pods have been tested
(pods 1 through 5).
Figure 3-34. Glitch Test Timing Waveforms
HP 1650B/1651B Performance Tests
Service Manual 3-27
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