Agilent Technologies HP 8566B Spécifications Page 286

  • Télécharger
  • Ajouter à mon manuel
  • Imprimer
  • Page
    / 405
  • Table des matières
  • MARQUE LIVRES
  • Noté. / 5. Basé sur avis des utilisateurs
Vue de la page 285
17.
20/30
Loop
Phase
Lock
Adjustments
Reference
RF-Section:
A10
20/30
Synthesizer
AlOAl PLLl VCO
AlOA3
PLLl
IF
AlOA4
PLL3 Up Converter
AlOA5
PLL2
VCO
A 1 OA8
PLL2
Discriminator
Description
Phase
Lock
Loop
1
(PLU):
On the AlOAl PLLl VCO Assembly, the
Loop Amplifier 40
kHz
LPF is first adjusted for
>65
dB
rejection of
the 50
kHz
subharmonics from fractional-n division. A frequency
synthesizer is used to inject a signal into the 40
kHz
LPF, and the filter
output is measured with a spectrum analyzer using a high-impedance
active probe. Then, the centering and tuning range of the
PLLl
VCO is checked and adjusted as required. On the
AlOA3
PLLl
IF
Assembly, the 140 MHz Lowpass Filter is checked and adjusted for
maximum rejection of mixing products between 160 MHz and 166
MHz. A synthesized sweeper is substituted for the
PLLl
VCO, and the
output of the
AlOA3
PLLl
IF Assembly is measured with a spectrum
analyzer.
Phase
Lock
Loop
2
(PLU):
On the
AlOA5
PLL2
VCO Assembly
and A10A8
PLL2
Discriminator Assembly, four interactive biasing
adjustments are used to set the centering and tuning range of the
PLL2
VCO.
PLL2
VCO biasing is adjusted by setting up proper voltage
levels at
AlOA8TP5
VCO TUNE and adjusting for corresponding
PLL2
VCO frequencies at AlOA5J4 (SCAN
1.1
MHz OUT). If
PLL2
will not
phase lock (PL2 UNLOCK indicated), the
AlOA6
PLL2 Phase Detector
Assembly is first disabled for coarse biasing adjustments. Fine biasing
adjustments of the
PLL2
VCO are made with the
AlOA6
PLL2
Phase
Detector Assembly installed. Then, span accuracy for narrow spans is
checked and adjusted by positioning the 100 MHz CAL OUTPUT signal
on the 9th CRT graticule line.
Phase Lock Loop
3
(PIL3):
On the
AlOA4
PLL3 Up Converter
Assembly, the 160 MHz BPF is adjusted for maximum output of the
1.6 Frequency Multiplier. The
PLL3
VCO biasing is then adjusted by
setting up proper voltage levels at
AlOA4TP3,
and the PLL3 VCO
output power level is verified.
3.146 Adjustments
Vue de la page 285
1 2 ... 281 282 283 284 285 286 287 288 289 290 291 ... 404 405

Commentaires sur ces manuels

Pas de commentaire