Agilent Technologies HP 8566B Spécifications Page 293

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17. 20/30 Loop Phase Lock Adjustments
Phase
Lock Loop
2
wJ4
Note
If
PLL2
is phaselocked, proceed to step 12. If
PLL2
will not phaselock
(PL2 UNLOCK indicated on CRT), start with step 1.
1. Set the RF Section LINE switch to STANDBY. Remove
AlOA6
PLL2
Phase Detector Assembly from its connector on the A23
Motherboard Assembly. It is not necessary to completely remove
the
AlOA6
PLL2
0 Detector Assembly from the RF Section.
2. Set the RF Section LINE switch to ON and press
@ZZQ
3. Disconnect the cable 7 (violet) from AlOA5J4 SCAN
I.1
MHz
OUT, and connect the frequency counter BNC input to AlOA5J4
using a BNC to SMB Snap-on Test Cable. Set
the
input selector
switch on the frequency counter to
(lo
HZ
-
500 MHZ), and set the
impedance switch to
150.
4. On the RF Section, key in
(STOP]
10 MHz,
&TART
FREQ)
8.600 MHz,
(SHIFT)
(MKR+
REF
LVL~,
SWEEP [j!ZZZj, TRACE A
[CLEAR-WRITE].
5. Connect the DVM to
AlOA8TP5
VCO TUNE. Refer to Figure 3-79
for the location of
AlOA8TP5
VCO TUNE.
Adjustments 3-153
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